Semiconductor devices or integrated circuits (ICs) can include millions of devices, such as, transistors. Ultra-large scale integrated (ULSI) circuits can include complementary metal oxide semiconductor (CMOS) field effect transistors (FET). Despite the ability of conventional systems and processes to fabricate millions of IC devices on an IC, there is still a need to decrease the size of IC device features, and, thus, increase the number of devices on an IC. Nevertheless, there are many factors that make the continued miniaturization of ICs difficult. For example, as the size of conductive lines, interconnects or vias (pathways between integrated circuit layers used to electrically connect separate conductive layers) decreases, electrical resistance increases.
Conventional integrated circuits utilize conductive lines, vias, and interconnects to connect structures (e.g., gates, drain regions, source regions) and conductive lines. For example, a via can connect a gate above the substrate to a conductor line in a metal 1 layer. Vias can also interconnect conductive lines. For example, a via can connect a conductive line in a metal 1 layer to a conductive line in a metal 2 layer. A via is typically a metal plug which extends through an insulative layer in a multilayer integrated circuit.
Vias and barrier layers are discussed in U.S. Pat. Nos. 5,646,448; 5,770,519; and 5,639,691; each of which are assigned to the assignee of the present application. A barrier layer can be used to protect the via and insulative layer from metal diffusion and the via and conductive line from electromigration (EM). The barrier layer can contribute significantly to resistance associated with the via metal.
Electromigration is the mass transport due to momentum exchange between conducting electrons and diffusing metal atoms. Electromigration causes progressive damage to the metal conductors in an integrated circuit. In general, metals are most susceptible to electromigration at very high current density and temperatures of 100° C. or more.
Advances in IC fabrication techniques have enabled the use of copper (Cu) conductive lines, interconnects, vias and other structures. Typically, copper material is subject to a furnace anneal at a temperature of 250–300° C. to achieve the grain sizes of appropriate size. Larger grain sizes result in fewer grain boundaries, which in turn result in lower resistance as well as greater reliability for the conductive lines, vias, interconnects and other structures.
The performance with respect to electromigration of copper conductive lines, vias, and structures can be enhanced with the use of alloys. For example, alloy elements such as tin (Sn), zinc (Zn), indium (In), calcium (Ca), chromium (Cr), zirconium (Zr), hafnium (Hf), and lanthanum (La) can be distributed throughout a conductive line, via or other structure to reduce electromigration. However, it is desirable to use as little alloy element as possible, because the presence of alloy elements increases the resistivity of the copper structure.
Blocking electromigration in copper material by clogging grain boundaries with alloy elements is dependent on copper grain size and alloy element diffusion kinetics. Generally, the alloy elements should not be distributed within the grains of the copper structure. Instead, it is desirable to diffuse the alloy elements so that the copper grain boundaries are effectively clogged, thereby reducing electromigration problems. At higher temperatures, alloy elements can be diffused into the copper grains. Accordingly, the alloy elements must be distributed in the copper material sufficiently to clog grain boundaries without affecting the copper grain structures for optimized performance.
It is a challenge to control copper grain growth and alloy distribution when forming copper lines and other structures. It is particularly difficult to control alloy element distribution if the alloy is introduced prior to copper grain growth.
Thus, there is a need to for a method of manufacturing an IC that distributes alloy elements uniformly and yet allows suitable copper grain growth. Further, there is a need for a conductive structure having large grain growth and uniformity of alloy distribution. Even further, there is a need to improve the formation of vias, interconnects, and lines. Yet further, there is a need for a method of forming a copper structure which has uniform alloy element distribution and large copper grain size.